Various tests are made to sort out initial failures and boost quality in processes for manufacturing semiconductor devices (See for example, JP-A-Hei 5(1993)-297076.) In semiconductor devices including DRAM memory cells for example, these semiconductor test processes include checks of AC, DC characteristics, and reading/writing on the memory cell, etc.
FIG. 1 is a block diagram showing the structure of the semiconductor device disclosed in JP-A-Hei 5(1993)-297076. The semiconductor device in FIG. 1, tests a first internal circuit 102, a second internal circuit 103, and a third internal circuit 104 controlled by a test control circuit 106. In the technology disclosed in JP-A-Hei 5(1993)-297076, a test-result output circuit 108 outputs test results from the second internal circuit 103 to an output terminal 101 through switching control via a MOS 110 connected to the input terminal 101.
In the technology disclosed in JP-A-Hei 5(1993)-297076, the test control circuit 106 stores expectation values for internal circuit (first internal circuit 102-third internal circuit 104) operation in advance, compares these expectation values with the internal circuit (first internal circuit 102-third internal circuit 104) test results and judges the test results by outputting the matching/mismatching information.
Besides the technology disclosed in JP-A-Hei 5(1993)-297076, other methods are known for finding initial failures in semiconductor devices (See for example, JP-A-2001-356147). In order to directly check whether there is a burn-in mode set signal and power for the burn-in test, the technology in JP-A No. 2001-356147 contains a detecting unit to sense if there is a burn-in mode set signal and power (supply) for the burn-in test, and a detection result storage region for storing the results from the detecting unit. This technology then decides whether or not a load is being applied to the semiconductor device during burn-in.
Semiconductor devices are being made ever more highly integrated in recent years so a test different from the above test (Hereafter called a stress test) applies a voltage higher than the normal voltage across the word lines and bit lines in the DRAM memory cell to screen for initial failures in the DRAM memory cell. This stress test is an extremely essential process in the overall semiconductor manufacturing process.